Transistor saturation occurs when excessive currents are applied to the bases of bipolar transistors, driving the collector-base diode into forward bias and thus injecting minority carrier into the base of the transistor. Removal of this charge from the base results in slow turnoff characteristics of the transistor. Saturation can thus degrade the performance of high-speed switching circuits.
In semiconductor circuits, the use of Schottky barrier diodes is a popular means of preventing transistor saturation. The Schottky barrier diode maintains a low voltage across the base-collector diode thus preventing this junction from becoming forward biased and saturating the transistor. The resulting semiconductor transistor circuit is known as a Schottky clamped transistor.
The effectiveness of the Schottky clamp is limited by the ideality factor of the barrier diode. The typical Schottky diode is formed by depositing a metal layer on a lightly doped N-type silicon material. Irregularities in the surface of the N-type material cause imperfections in the metal to N-type silicon contact. These imperfections in the metal to N-type silicon contact contribute to nonideality.
In typical fabrication processes, a polysilicon layer which has been deposited over the surface of the semiconductor is etched away at the desired location to expose the N-type single crystal material. Due to the ever decreasing size of semiconductor circuits, the area of the barrier diode and thus the area to be etched away continues to decrease in size. The limited area to be etched in present day circuits precludes the use of a wet etch process and a dry etch process must be used.
Both the polysilicon to be etched away and the underlying doped silicon material have the same chemical composition. Thus, there is no way in the typical etching process to determine by end point detection where the polysilicon material ends and the underlying single crystal N-type material begins. Therefore, a timed etch process is used whereby the etch proceeds for the period required to etch away the polysilicon material as calculated from the thickness of that material.
This timed etching process contributes to irregularities in the surface of the N-type silicon region in two respects. First, the timed etch process is somewhat imprecise and the etching process occasionally extends past surface of the single crystal N- material. Second, the dry etch process is associated with some mechanical sputtering due to bombardment by gas molecules and this action can cause damage to the N-type single crystal silicon structure when this area is exposed to the gas. The resulting surface irregularities negatively impact the ideality of the barrier diode.
A further complication resulting from the typical fabrication process negatively impacts semiconductor performance. Due to misalignment of Schottky contact mask the typical fabrication process can leave an amount of intrinsic polysilicon material (normally etched away) adjacent the diode. See FIG 17. A parasitic Schottky diode develops where metal comes into contact with intrinsic polysilicon material which could be a source of leakage current.